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Raymond J. Andraka, P.E.
the Andraka Consulting Group, Inc.
202 Torrie Lane. North Kingstown, RI 02852-1688
401/884-7930 FAX 401/884-7950
EDUCATION:
M.S.E.E., University of Massachusetts, May 1992.
B.S.E.E., Lehigh University, January 1984.
Registered Professional Engineer, Rhode Island License 6591
Xilinx Certified Consultant, XPERTs partner
SKILLS SUMMARY:
FPGAs: Over 100 FPGA designs in Actel, Altera, Atmel, and Xilinx
FPGAs.
High Performance Signal Processors:
Radar, digital communications physical system modeling, imaging, video, audio,
reconfigurable computing.
Tools: Matlab, VHDL & Verilog, Synplicity,
Aldec, Modelsim,
assorted FPGA place and route tools.
EMPLOYMENT HISTORY:
July 1994- present President, the Andraka Consulting Group, Inc., North
Kingstown, RI. High performance FPGA design for DSP
applications.
June 1993-April 1995 Sr. Engineer, G-Tech Corporation, West Greenwich RI. Image
readers and terminals for lottery systems.
May 1988-June 1993 Sr. Engineer, Raytheon Missile Systems Division, Digital Systems
Laboratory, Tewksbury MA. Radar signal processors, guidance computers.
Dec 1985-May 1988 Captain, USAF. Rome Air Development Center, Hanscom AFB, MA. Signals
analysis algorithm development
Feb 1984-Dec 1985 1st Lt, USAF. Electronic Systems Division, Hanscom AFB, MA. Program
management, LF communication systems
EXPERIENCE:
· Numerous FPGA and board level designs for Radar
signal processors including: Doppler pulse pair processors (averaged correlations at
10Mhz), Logarithmic IQ to polar (40Mhz), Digital quadrature demodulation, matched
filters, polynomial curve fitting, several CORDIC vector processors, IQ correction,
correlators, and frequency domain filters. FPGA processors implemented in Xilinx,
Atmel, Actel and Altera devices.
· Real-time high fidelity Radar environment simulation
using FPGAs. Hardware sorting, accurate gaussian and gamma noise modelling,
quadrature NCO's, pulse compression, polynomial compression and decompression.
· Several reconfigurable processor board designs using
Xilinx, Atmel and National Semiconductor FPGAs. These boards are used in radar and
video applications. All are 1st pass successes.
· Digital communications FPGA designs including 16 channel
80Mhz serial I/O, ethernet controller interface, digital modulation/demodulation (QAM 16,
FSK, QPSK).
· Imaging and video processors in FPGAs including scan
conversions, filtering, feature extraction, population counting, image combining and
overlays.
· DSP macros for FPGAs including first publicized FIR
filter, CORDIC processors, Log converters, limiters, sorting and search engines, fast
multipliers, and floating point conversions.
· Several LCD and CRT display controllers in Xilinx
FPGAs.
· Many other board level and FPGA designs, including
image readers, smart card controllers, point of sale terminals, DPLLs, medical machine
controllers, microcoded computers.
SERVICE:
· PLDCon'97 Reconfigurable Computing Technical
Session Chairman
· DesignTech'98 FPGA Session moderator
· ACM/SIGDA FPGA'99 Conference Program Committee
PUBLICATIONS:
· "FIR filter fits in an FPGA using a bit
serial approach," Proceedings of the Third Annual PLD Design Conference and Exhibit,
March 1993.
· "Building a High Performance Bit Serial Processor in
an FPGA," Design SuperCon ‘96., January 1996.
· "A Dynamic Hardware Video Processing Platform,"
Proceedings of SPIE Photonics East ‘96, Conference on Reconfigurable Technology for
Rapid Product Development and Computing, November 1996.
· "A survey of CORDIC algorithms for FPGAs,"
ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 1998.
· "Reconfigurable Computing Session" Proceedings
of PLDCon’97 Conference and Exhibit, April 22, 1997.
· "Digital Modulation and Demodulation Techniques for
FPGAs" Techforum (tutorial session), DesignCon98, January 1998 and DesignCon99,
February 1999.
· "Reconfigurable Architectures Seminar," WESCON '98 , September 1998.
· "An FPGA based processor yields a real time high
fidelity radar environment simulator," Military
and Aerospace Applications of Programmable Devices and Technologies Conference,
September 1998.
· Featured in article by Brian
Dipert, "Shattering the Programmable Logic Speed Barrier", EDN, May 22,1997
issue.
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