Public repository for the frequently asked questions (FAQs) for designers of systems using FPGAs. The contributors to this site are typically also participants in the comp.arch.fpga news group.
Online FPGA Sources:
Avnet Marshall price and availability
opencores.org A growing library of freeware and shareware cores for common functions..
Neat tricks, techniques:
DSP Guru's DSP tricks
MIT's AI lab collection of computer
hacks (html reprint)
The DSPStore A one stop shop for DSPalgorithms, books, devices, software, boards, tools, utilities, etc
Interesting Articles about DSP in FPGAs by other authors
Soft Radios and Modems on FPGAs Les Mintzer, Communication System Design, February 2000
Hardware Implementations of Digital Multirate Filters Tony San, Communication System Design, April 2000
Moving Data across Asynchronous Clock Boundaries Peter Alfke, Integrated System Design, 2000
citeseer.nj.nec.com is quite a good resource
for DSP papers. It's mainly a citation database, but it has downloadable copies of
a lot of the papers too.
Algorithms and Number Theory
square root algorithm
Randy Yates' fixed point arithmetic pages
Practical Considerations in Fixed-Point FIR Filter Implementations discusses The effects of fixed point arithmetic on FIR filter performance
Linear Feedback Shift Registers
Maximal Length LFSR Feedback Terms A catalog of Maximal length sequences to 39 bits for LFSRs
Xilinx application note XAPP052 - Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators
CRC code generator generates VHDL and Verilog for arbitrary CRC polynomials and data bus widths.
Any time you have two asynchronous clocks in a system, you have a probability of suffering a metastable event. Learning to deal with it correctly makes the difference between a system that will caus etrouble or on that works. Phillips Semiconductor has a decent primer on metastability in the form of an application note.
Digital Phase Lock Loops
Actel application note s04_18 shows some of the basics for a DPLL implemented in FPGAs
VHDL tips, tutorials, etc
for generating bit_vector from boolean expression
Doll's VHDL Verification Course