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Packaged CORES: These packaged COREs are drop in solutions delivered through the Xilinx CORE generator. They are Relatively Placed Macros (RPMs), completely pre-placed to guarantee timing, implementation and fit. Normal delivery includes the edif netlist, VHDL, Verilog and schematic templates for instantiation into your design, and VHDL behavioral models. Source is available for additional cost SMPTE 292 (Bit Serial HD-TV) Scrambler and Descrambler Cores A set of Xilinx cores for SMPTE 292 (Bit Serial High Definition Television) scrambling, descrambling and framing. These placed COREs work with AMCC's S8401/S8501 serializer and deserializer chipset. The transmit CORE converts transmit data to the scrambled NRZI format in 20 bit parallel format to be serialized by an AMCC S8401. The receive core accepts scrambled NRZI data from and AMCC S8501in 20 bit parallel format, descrambles the data, detects frame sync and aligns the received data to the 20 bit output. The Core macros are designed for the Xilinx 4K (and Spartan) architecture, and will work in 4000E-2, 4000XL-1,4000XLA,and 4000XV or faster parts at the required 74.25 MHz. More detail is available in the datasheet ( XC4000 version). Call or email for more information and pricing.
VHDL simulation models available at no cost for the receive and transmit cores (these are not synthesizable). Call or email for more information.
Virtex 4 in -11 speed grade runs at 330 MS/sec -- Ultra-fast 8 and 16 point FFT cores (under 50 ns transform time)
See the data sheet for more details
Intellectual Property Andraka consulting has developed an impressive collection of intellectual property for DSP applications, which although are not productized for stand-alone sale, can be drawn upon for a custom design. The following is a partial list of IP developed by Andraka Consulting Communications IP
Video & Imaging IP
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