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Andraka Consulting Group, Inc.  "the high performance FPGA design specialist"  

COREs and IP

 
     
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Packaged CORES: These packaged COREs are drop in solutions delivered through the Xilinx CORE generator.  They are Relatively Placed Macros (RPMs), completely pre-placed to guarantee timing, implementation and fit.  Normal delivery includes the edif netlist, VHDL, Verilog and schematic templates for instantiation into your design, and VHDL behavioral models. Source is available for additional cost

SMPTE 292 (Bit Serial HD-TV) Scrambler and Descrambler Cores

A set of Xilinx cores for SMPTE 292 (Bit Serial High Definition Television) scrambling, descrambling and framing.  These placed COREs work with AMCC's S8401/S8501 serializer and deserializer chipset

The transmit CORE converts transmit data to the scrambled NRZI format in 20 bit parallel format to be serialized by an AMCC S8401.  The receive core accepts scrambled NRZI data from and AMCC S8501in 20 bit parallel format, descrambles the data, detects frame sync and aligns the received data to the 20 bit output.

The Core macros are designed for the Xilinx 4K (and Spartan) architecture, and will work in 4000E-2, 4000XL-1,4000XLA,and 4000XV or faster parts at the required 74.25 MHz.  More detail is available in the datasheet ( XC4000 version).   Call or email for more information and pricing.

The Core macros are now also available for SpartanII, VIrtex and Virtex-E Families.  They will fit in XCV30 or larger devices, and meet the 74.25 MHz timing for all speed grades.  See the datasheet (virtex version) for details.  Call or email for more information and pricing.

VHDL simulation models available at no cost for the receive and transmit cores (these are not synthesizable).  Call or email for more information.

Now Available for Virtex2, Virtex2Pro and Virtex4

Virtex 4 in -11 speed grade runs at 330 MS/sec --

Ultra-fast 8 and 16 point FFT cores (under 50 ns transform time) 

bulletHighly Optimized Virtex Core
bulletFits in XCV100  - core fits in a 20h x 25w  CLB rectangle
bulletHalf the size of the Xilinx COREgen core
         973 slices vs. 1386 slices in Xilinx core
bullet40% faster than Xilinx COREgen core  
         >133MHz vs  ~95 MHz in Virtex -4 speed grade parts
       > 330 MHz in Virtex4 -11 speed grade parts
        > 280 MHz in Virtex 2 Pro -6 speed grade parts
bulletLess than 70 ns transform time in VirtexE-8 (230+ MHz sample clock)  
bullet16 bit complex input and output data
bulletNaturally ordered input and output data
bulletData may be streamed continuously
bulletOne sample on every clock
bulletRelatively Placed Macro guarantees density and performance
bulletNo Block RAM used (available for use as reorder memory for larger FFTs)
bulletNo embedded multipliers used (available for other DSP functions)
bulletUsable in devices with no available embedded multipliers!

 

See the data sheet for more details

Intellectual Property Andraka consulting has developed an impressive collection of intellectual property for DSP applications, which although are not productized for stand-alone sale, can be drawn upon for a custom design.  The following is a partial list of IP developed by Andraka Consulting

Communications IP

bulletComplex digital down-converters
bulletVarious demodulators
bulletPolyphase channelizing filter banks
bulletLarge FFTs
bulletQuadrature NCO’s and mixers
bulletCORDIC magnitude and phase conversions
bulletCORDIC vector rotators
bulletPolyphase resampling (fractional rate change) filters.
bulletCIC filters, parameterized for M, N, R
bulletLogarithms in arbitrary bases to ½ dB
bulletSorting and search engines
bulletMatched filters
bulletFast convolution

Video & Imaging IP

bulletSMPTE-292 HDTV scrambler/descrambler core set
bulletHistograms
bulletEdge (Sobel) operators
bulletDilate/Erode
bullet2D filters
bulletAbsolute differencing, thresholding
bulletMotion detection
bulletScan conversion (polar to raster)
bulletColor space conversion

 

 
 
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Last modified: March 16, 2007